Through Silicon Via (TSV) technology is an emerging solution for connection of stacked semiconductor integrated circuit (IC) chips. Very wide busses are possible because the TSV density can be much higher than conventional pads for wire bonding. Normal bonding pads for wire bonds have planar dimensions of around 100 um while TSVs may be 10 um or even smaller. Connecting a bus between a number of stacked chips is straightforward because the connection is made vertically between each chip in a stack of chips. FIG. 1 shows the cross section of a TSV structure in a single integrated circuit die before wafer stacking. The TSV extends from the bottom of the chip through the silicon substrate and through the layers of active circuitry and interconnect. A pad is located at the top and bottom surface of the die electrically connected to the TSV. Finally, a solder ball is attached to the top pad.
A process for manufacturing TSVs is described in the paper “Through-Silicon Via (TSV)” by Makoto Motoyoshi published in the Proceedings of the IEEE vol. 97, no. 1, January 2009, incorporated herein by reference. First, the semiconductor circuit is fabricated on a silicon wafer using well known processes to complete the active circuit and interconnect layers, including the top layer bonding pads. The wafer may then be polished on the back side to reduce the thickness. The top side of the wafer may be bonded to a handle wafer to provide mechanical support during subsequent polishing and TSV process steps, and to protect the active circuit and interconnect layers. Then a photoresist layer is applied to the back surface of the wafer and the areas where TSVs are to be defined. A deep silicon etch process and successive reactive ion etch (RIE) processes create through holes extending from the back of the wafer, through both the substrate and the active circuit and interconnect layer to expose the bottom of the top side bonding pads. The etch process is stopped by the metal bonding pad. Then a side wall insulator within the through holes is formed using low-temperature plasma-enhanced chemical vapor deposition (PECVD) SiO2. This prevents the TSV from shorting to the substrate. A further RIE process removes the SiO2 from the bottom of the top side bonding pad to allow the TSV contact. A contact metal layer and/or a diffusion barrier metal layer may be deposited in the through hole at this stage. The through hole is then filled with conductive material such as a conductive paste or through a process such as plating or metal CVD. The final step is deposition of metal on the bottom of the wafer and formation of bottom bonding pads. The handle wafer is then removed and solder balls are attached to the top bonding pads.
The chip stack is assembled by positioning one die on top of another, with respectively corresponding TSVs aligned along the TSV axes (resulting in axially aligned TSVs), and raising the temperature to melt the solder ball material. FIG. 2 shows a cross section of two stacked chips with TSV interconnection. The process may be repeated to stack more chips.
The vertical TSV interconnect shown in FIG. 2 is useful for bus interconnection where every chip is connected in the same way to the same set of TSVs. Memory chips may be connected in this way to common address, data, and control busses as shown (see page 130) in the paper “8 Gb 3D DDR3 DRAM using Through Silicon Via Technology”, by Kang et. al., published in the ISSCC Digest of Technical Papers, February 2009, and incorporated herein by reference. However, a problem remains in stacking bussed memory chips that are each indistinguishable from one another. That is, the problem of uniquely identifying each chip so that commands such as read and write are only executed by a single chip in the stack. In conventional printed circuit board memory subsystems or wire-bonded multi-chip packages, typically a unique chip enable signal CE is sent to each device sharing a bus to identify which chip is being addressed and which chip has control of the databus. This approach does not work in stacked memory devices which are connected only with continuous vertical TSVs.
United States Patent Application Publication 2009/0127668, incorporated herein by reference, provides a solution to this problem. In a stack of common die with TSVs, every other die is rotated by 180° to provide a serial TSV connection that passes through intervening circuitry on each die. A disadvantage of this solution is that TSVs must be located symmetrically about the axis of rotation of the chip, which is typically the geographical center of a rectangular die. This reduces the flexibility in placement of TSVs and may lead to a die size penalty. Some memory devices such as NAND flash have pads located along one edge of the die which would preclude this approach.
United States Patent Application Publication 2009/0161402, incorporated herein by reference, discloses a similar method of making serial TSV connections through die rotation. Instead of a memory bus with common connections to all die within the stack, a serial point-to-point daisy-chained ring configuration is used. United States Patent Application Publications 2007/0233917, 2007/0234071, and 2008/0155219, all of which are incorporated herein by reference, disclose several alternatives for device ID assignment in a serial point-to-point daisy-chained ring topology. The serial point-to-point daisy-chained ring configuration has a disadvantage in that the ring cannot be completely connected using TSVs. In particular, wire bonds are required to connect the top die of the stack to the package substrate in order to pass data back to the controller.
US Patent Publication 2007/0165457, incorporated herein by reference, discloses a serial point-to-point topology with an upstream path and a downstream path passing through each memory device. The top device does not have a direct connection back to the controller, so the aforementioned bonding wires are not required. However, assuming all of the stacked memory devices are identical, the last device would have unconnected inputs to the downstream links to the controller. These unconnected inputs may pick up random noise, thus causing unnecessary logic transitions, and thus unnecessary power dissipation, on each downstream link.
It is desirable in view of the foregoing to provide for stacked arrangements of connected integrated circuits that avoid disadvantages such as described above.